Speculative execution is the processor's capability to execute instructions in advance of the
actual program counter. The processors dispatch/execute unit uses data flow analysis to
execute all available instructions in the instruction pool and store the results in temporary
registers. A retirement unit then searches the instruction pool for completed instructions that
are no longer data-dependent on other instructions to run or that have unresolved branch
predictions. If any such completed instructions are found, the results are committed to memory
by the retirement unit or the appropriate standard Intel architecture in the order they were
originally issued. They are then retired from the pool.
Dynamic execution essentially removes the constraint and dependency on linear instruction
sequencing. By promoting out-of-order instruction execution, it can keep the instruction units
working rather than waiting for data from memory. Even though instructions can be predicted
and executed out of order, the results are committed in the original order, to avoid disrupting or
The dual independent bus (DIB) architecture was another innovation that was first implemented
in the sixth-generation processors from Intel and AMD. DIB was created to improve processor
bus bandwidth and performance. Having two (dual) independent data I/O buses enables the
processor to access data from either bus simultaneously and in parallel rather than in a singular
sequential manner (as in a single-bus system). The main (often called front-side) processor bus is
the interface between the processor and the motherboard or chipset. The second (back-side) bus
in a processor with DIB is used for the L2 cache, enabling it to run at much greater speeds than if
it shared the main processor bus.
actual program counter. The processors dispatch/execute unit uses data flow analysis to
execute all available instructions in the instruction pool and store the results in temporary
registers. A retirement unit then searches the instruction pool for completed instructions that
are no longer data-dependent on other instructions to run or that have unresolved branch
predictions. If any such completed instructions are found, the results are committed to memory
by the retirement unit or the appropriate standard Intel architecture in the order they were
originally issued. They are then retired from the pool.
Dynamic execution essentially removes the constraint and dependency on linear instruction
sequencing. By promoting out-of-order instruction execution, it can keep the instruction units
working rather than waiting for data from memory. Even though instructions can be predicted
and executed out of order, the results are committed in the original order, to avoid disrupting or
The dual independent bus (DIB) architecture was another innovation that was first implemented
in the sixth-generation processors from Intel and AMD. DIB was created to improve processor
bus bandwidth and performance. Having two (dual) independent data I/O buses enables the
processor to access data from either bus simultaneously and in parallel rather than in a singular
sequential manner (as in a single-bus system). The main (often called front-side) processor bus is
the interface between the processor and the motherboard or chipset. The second (back-side) bus
in a processor with DIB is used for the L2 cache, enabling it to run at much greater speeds than if
it shared the main processor bus.